Generally, a motor needs an inverter drive to control the rotor frequency of the motor and regulate the rotation speed of the motor, so as to drive the motor to operate. In order to increase the safety of the motor during the operation period, a parallel inverter drive system has been proposed. The parallel inverter drive system is made up of a plurality of inverter drives with their outputs being connected in parallel with each other, thereby driving the motor. The parallel inverter drive system is different from the conventional inverter drive system in that the parallel inverter drive system is made by substituting the bulky inverter drive with a number of small-volume inverter drives and allowing these small-sized volume inverter drives to output collaboratively for driving motor. The main features of the parallel inverter drive system are focused on modularity and redundancy. The modularity feature means that the controllers for individual inverter drives with small capacity are independent from other inverter drives. Thus, the user can expand or lessen the capacity of the inverter drive system depending on user's demands. The redundancy feature means that in case of malfunction, the damaged inverter drive can be replaced during the operation of the inverter drive system without overhauling the entire system. If the inverter drive system is appropriately designed, the motor can be driven to operate continuously on the condition that the other undamaged inverter drives are operating normally, while the damaged inverter drives are replaced without the need of shutting down the entire system. Nonetheless, as errors are existed among the individual inverter drives in the parallel inverter drive system, the currents of the inverter drives are not outputted to the motor in their entirety. Under this condition, currents are flowing among inverter drives. Such phenomenon is termed a circulating current. The error among the inverter drives that induces the circulating current may be the asynchrony of the pulse-width modulation (PWM) carrier waves, the asynchrony of the voltage commands, the system parameters, or the mismatch of the external reactors.
A contemporary technique for suppressing the circulating current in a parallel inverter drive system is accomplished by the detection of zero-sequence current. Using this technique, the detected zero-sequence current is used to change the duty cycle of the zero-voltage vector to allow the zero-sequence current of the slave inverter drive to be zero (certainly the zero-sequence current of the master inverter drive is also zero under this condition). Therefore, the circulating current is suppressed. Although the technique of changing the duty cycle of the zero-voltage vector by the detected zero-sequence current can suppress the circulating current, such technique has the following drawbacks. First of all, such technique can address the problem that the zero-sequence is not zero. However, the fact that the zero-sequence current is zero does not indicate that the circulating current is zero. Hence, such technique may allow the circulating current to linger even after the zero-sequence current is subdued. Second of all, such technique needs to adjust the duty cycle of the zero-voltage vector in a real-time manner. Hence, the micro-controller unit (MCU) of the controller in the parallel inverter drive system must support the function of dynamically adjusting the duty cycle signal. In this manner, the hardware arrangement of the parallel inverter drive system is constrained, and the cost of the parallel inverter drive system is hard to be controlled. Finally, such technique is feasible on the condition that the parallel inverter drive system is consisted of two inverter drives. If the parallel inverter drive system is consisted of three or more inverter drives, such technique does not disclose the operating mode of achieving circulating current suppression in such parallel inverter drive system.
Referring to FIG. 1, which is an operative block diagram of a parallel inverter drive system using the circulating current suppression technique with zero-sequence current detection according to the prior art. As shown, the parallel inverter drive system of FIG. 1 includes two parallel-connected inverter drives INV_1 and INV_2, in which the inverter drive INV_1 is a master inverter drive and the inverter drive INV_2 is a slave inverter drive. Va1*, Vb1*, Vc1* are the voltage commands inputted into the inverter drive INV_1, and Va2*, Vb2*, Vc2* are the voltage commands inputted into the inverter drive INV_2. The master inverter drive INV_1 includes a space-vector modulation (SVM) controller 102 for converting the voltage commands Va1*, Vb1*, Vc1* into duty cycle signals Ta1*, Tb1*, Tc1*, and includes a switch device 104 being driven by the duty cycle signals Ta1*, Tb1*, Tc1* and a duty cycle signal T01 with a zero-voltage vector to conduct switching operations. Thus, an AC output voltage and an AC output current are generated to drive the motor 106. Likewise, the slave inverter drive INV_2 includes a space-vector modulation (SVM) controller 108 for converting the voltage commands Va2*, Vb2*, Vc2* into duty cycle signals Ta2*, Tb2*, Tc2*, and includes a switch device 110 being driven by the duty cycle signals Ta2*, Tb2*, Tc2* and a control signal derived by adding a duty cycle signal T02 with a zero-voltage vector with an adjustment quantity K to conduct switching operations. Thus, an AC output voltage and an AC output current are generated to drive the motor 106. It is noteworthy that if the duty cycle signal T01 with a zero-voltage vector is zero, the space-vector modulation (SVM) controller 102 can be replaced with a sinusoidal pulse-width modulation (SPWM) controller. In this example, the operation of the slave inverter drive INV_2 is adjusted along with the operation of the master inverter drive INV_1. The slave inverter drive INV_2 includes an adder 112 for totaling the feedback currents of the slave inverter drive INV_2 to generate a summation current I0. The summation current I0 is subtracted with a signal with a current value of 0 by subtractor 114, and the output of the subtractor 114 is outputted to a proportional integrator (PI) 116. The proportional integrator 116 is used to convert the summation current I0 into an adjustment quantity K. An operator 118 is used to adjust the duty cycle signal T02 with a zero-voltage vector by the adjustment quantity K. The output of the operator 118 is outputted to the switch device 110 to control the switching operations of the switch device 110. Hence, with the adjustment of the summation current I0, the adjustment quantity K represents the dynamic change of the duty cycle signal T02 with a zero-voltage vector. It can be understood from FIG. 1 if the system includes a multiplicity of slave inverter drives, the index for calculating the control quantity (i.e. the summation current I0) can not be carried out.
A second solution to suppress the circulating current in a parallel inverter drive system is accomplished by a current sharing method to allow the phase output currents of the inverter drives to be equal with each other. Thus, the current flowing among the inverter drives is suppressed. Using such technique can efficiently balance the output currents of the inverter drives and prohibit the output currents of the parallel-connected inverter drives from interflowing with each other. Such technique is advantageous in that such technique is irrelevant to the space-vector pulse-width modulation (SVPWM), and thus the complicated calculation for generating the duty cycle signal of the zero-voltage vector and the function of dynamically adjusting the duty cycle signal of the zero-voltage vector are not necessary. Nonetheless, such technique still has the following drawbacks. First of all, such technique is antithetical to the aforementioned circulating current suppression technique using the detected zero-sequence current. That is, such technique can not theoretically guarantee that the zero-sequence current is zero even if the output current of the inverter drives are all equal. Second of all, such technique can be applied to a PWM-based control configuration, e.g. such technique can be applied to a sinusoidal pulse-width modulation (SPWM) configuration. However, such technique can not be appropriately linked with the space-vector pulse-width modulation (SVPWM) configuration. However, the inverter drives are generally required to operate under the space-vector pulse-width modulation (SVPWM) mode in practical applications for the purpose of improving voltage utilization. This would cause inconvenience if such technique is applied to the parallel inverter drive system.
Referring to FIG. 2, which is an operative block diagram of a parallel inverter drive system using the circulating current suppression technique with current sharing configuration according to the prior art. As shown, the parallel inverter drive system for driving a motor 106 is consisted of parallel-connected inverter drives INV_1, . . . , INV_n. Each inverter drive is configured to receive a three-phase voltage command (Va1*, Vb1*, Vc1*), . . . , (Van*, Vbn*, Vcn*). Each inverter drive includes a sinusoidal pulse-width modulation (SPWM) controller 201, and a switch device 200 connected to the sinusoidal pulse-width modulation (SPWM) controller 201. Each inverter drive includes a current averager Ave for obtaining the output currents of other inverter drives and calculating the average current of the output currents of all the inverter drives. The average current calculated by the current averager Ave is transmitted to the operator 202. The operator 202 is configured to compare the output current of the local inverter drive with the average current calculated by the current averager Ave, and in response thereto outputting an error value. A gain controller P is used to calculate a compensating voltage command for compensating the output current according to the error value. The compensating voltage command will be fed back to the sinusoidal pulse-width modulation (SPWM) controller 201, and an operator 203 is used to perform arithmetical operations to the three-phase voltage command (Va1*, Vb1*, Vc1*), . . . , (Van*, Vbn*, Vcn*) and the compensating voltage command, thereby generating a compensated three-phase voltage command. As can be understood from FIG. 2 that the feature of using a current sharing configuration to accomplish the circulating current suppression is that each inverter drive INV_1, . . . , INV_n receives a respective compensated voltage command to force each inverter drives INV_1, . . . , INV_n to have the same phase current with the average current (each phase has different average current to follow). Also, the current sharing configuration of FIG. 2 can be applied to the same control mechanism regardless of the number of the inverter drives. Nevertheless, the generation of the three-phase voltage command is actually accomplished under the sinusoidal pulse-width modulation (SPWM) mode as mentioned above. Also, the respective compensation topology for the phase current can not deal with the problem that the zero-sequence current may exist.
The third solution to suppress the circulating current in a parallel inverter drive system is accomplished by a current droop method. Such technique does not require each inverter drive to exchange current information with each other. Instead, such technique requires each inverter drive to compensate its phase current to enhance the modularity of the inverter drive. Referring to FIG. 3, which shows an operative block diagram of a parallel inverter drive system using the circulating current suppression technique with current droop configuration according to the prior art. Compared to the circuit topology of FIG. 2, the circuitry of FIG. 3 does not does not require each inverter drive to exchange current information with each other. Instead, the circuitry of FIG. 3 requires each inverter drive to compensate its phase current. Hence, the output phase current of each inverter drive is provided to the gain controller P for calculating a compensating voltage command for the output phase current. The compensating voltage command is fed back to the sinusoidal pulse-width modulation (SPWM) controller 201. The operator 203 is used to perform arithmetical operations to the three-phase voltage command (Va1*, Vb1*, Vc1*), . . . , (Van*, Vbn*, Vcn*) and the compensating voltage command, thereby generating a compensated three-phase voltage command. Nonetheless, such technique has the following drawbacks. First of all, such technique can result in similar output currents for the inverter drives only on the condition that the each inverter drive INV_1, . . . , INV_n has similar parameters with each other. In other words, the current sharing effects can be attained effectively on the condition that each inverter drive INV_1, . . . , INV_n has the same specification with each other. Second of all, if the method of phase current compensation is used, the compensation quantity will be large if the phase current is large. When the rotation speed of the motor 106 is increasing, a relatively large current will be outputted. Under this condition, if the current droop technique is used, the relatively output current will be subdued. Thus, the transient response will be damped to slow down the acceleration of the rotation speed of the motor. Finally, such technique can simplify the current sharing configuration and attain a better modularity. However, the aforementioned drawbacks are still unresolved.